The technology of inter-process communication (IPC) in which, when plural pieces of software perform processing in cooperation with each other, data used by each piece of software is transmitted and received is conventionally known. As an example of a technique for such inter-process communication, a technique using queues for inter-process communication is known.
An information processing system includes a plurality of nodes that include respective individual central processing units (CPUs). Technology of a multi-node system is known in which a plurality of CPUs perform respective different processes. As an example of such technology of a multi-node system, there is known an information processing system in which a plurality of CPUs having the function of caching data are included and the CPUs perform respective different processes at the same time. Furthermore, technology of a shared memory system is known in which CPUs execute operating systems (OSs) independent of each other, respectively, and part of a memory region is shared by the CPUs. With such a configuration, it is possible to increase the capacity more. In addition, since an OS individually operates on each node, errors may be stopped from spreading. This makes it possible to improve the availability of the system.
Each node includes a local memory, hypervisor (HPV) software, an OS, and a device driver and performs user processes different from each other at the same time. Note that the HPV software is software that manages virtual machines run by the nodes. In such an information processing system, a write pointer and a read pointer are stored in a shared memory shared by the nodes, thus implementing a queue. Inter-process communication of user processes is thus performed between nodes.
A transmitting-side node in inter-process communication is provided with a transmission message register dedicated to each core or thread. Using application software executed by a CPU of the transmitting-side node, a message is written to a transmission message register and the written message is transmitted to a receiving-side node. The message transmitted contains an identifier (ID) of a CPU of the destination and a register set ID.
The receiving-side node is provided with an address register, a read pointer, a write pointer, and a register set including a plurality of entries. The receiving-side node writes a message in a storage region indicated by entry information of a register set selected by the register set ID designated by the transmitting-side node.
Here, the ways in which a user process of the receiving-side node detects message reception include two ways: polling monitoring and a message received interrupt.
In the case where polling monitoring is performed, a user process carries out checks for message reception at regular intervals regardless of the presence or absence of reception of a message. Then, the user process, when detecting a message during a check for message reception, performs a process of reading a message.
In the case where a message received interrupt is performed, the user process on the receiving side is in a sleep state. Then, upon receiving an interrupt request from a CPU, the user process performs a context switch and performs the process of reading a message. Japanese Laid-open Patent Publication No. 2013-214168 is an example of this kind of related art techniques.
However, in a message received interrupt technique, a CPU issues an interrupt request each time a message is received. Specifically, the CPU of the receiving-side node, upon receiving a message, sets an interrupt factor in a register set and issues an interrupt request to a user process.
Here, when the number of entries of a register set of a message receiving circuit is large, that is, when the number of messages that may be received is large, the number of issued interrupt requests is increased. Information of a register set is recorded on a high-capacity medium such as a random access memory (RAM). Consequently, it takes time to search for interrupt factors stored in the register set, and it takes much time to perform an interrupt reap process in which interrupt factors are collected.
In view of the above, the techniques of this disclosure are directed to providing an information processing device, an information processing system, and an interrupt device control method for performing an interrupt reap process at high speed.